RISC-V development environment for TensorFlow Lite models

Problem definition

For production deployment of AI, e.g. in industrial plants or mobile systems, it is often necessary to port the AI implementation to edge devices. However, available off-the-shelf systems are not always suitable: Often they do not satisfy the contradicting demands on performance, energy consumption or operating conditions.

Goal

Tool support for the selection or design of system-on-chip (SoC) platforms that are tailored to the AI implementation as well as the operating conditions.

Solution expertise

Development environment for application-specific design of RISC-V-based SoC architectures. Building on top of a RISC-V hardware generation framework, an application-specific SoC accelerator architecture is generated.

Test bed

FPGA-based SoC architectures for time series analysis prepared for synthesis.